Utafiti huu unachunguza muundo mpya wa MOSFET ya silicon carbide yenye trench isiyolingana, unaounganisha transistor ya uga ya junction iliyo normally-off (junction field-effect transistor, JFET) na njia mbili sambamba za uendeshaji wa mbele ndani ya cell moja. Muundo unaoitwa IJDC-ATMOS umelinganishwa na C-ATMOS, ambayo ni MOSFET ya kawaida ya asymmetric trench, kwa kutumia numerical device simulations za Sentaurus TCAD. Katika matokeo ya simulation, specific on-resistance ya IJDC-ATMOS imepungua kutoka 2,49 mΩ·cm² hadi 1,69 mΩ·cm², reverse-conduction cut-in voltage kutoka 2,82 V hadi 1,76 V, na total switching loss kutoka 4,27 mJ/cm² hadi 2,26 mJ/cm². Hata hivyo, study inategemea numerical simulation pekee; hakuna physical device fabrication, electrical measurement, long-term reliability test au validation katika real power converter iliyofanywa.

Sifa kuu ya muundo uliopendekezwa katika forward conduction ni kwamba channel ya kwanza Ch1 kwenye trench sidewall na planar channel ya pili Ch2 chini ya trench hufunguka kwa wakati mmoja na kuunda njia mbili sambamba kwa electrons. Katika reverse conduction, normally-off JFET channel hutoa unipolar current path inayofunguka kabla ya parasitic body diode. Kwa mujibu wa simulations za authors, mechanism hii hupunguza hole injection katika body diode na risk ya bipolar degradation inayohusiana nayo, huku pia ikipunguza reverse-recovery charge.

Kwa mtazamo wa Uturuki: Study inaweza kutoa mfano wa kimetodolojia kwa research na design work nchini Uturuki katika SiC power semiconductors zinazotengenezwa kwa electric-vehicle power electronics, renewable-energy converters, industrial drives, aviation electronics na high-voltage switching systems. Ili kutathmini applicability ya muundo nchini Uturuki, local TCAD models zinapaswa kucalibrateiwa kwa material na interface parameters, manufacturability analysis ifanywe, real 4H-SiC devices zitengenezwe, static na dynamic electrical measurements zirudiwe, na high-temperature pamoja na long-term reliability experiments zifanywe. Kutokana na study hii haiwezi kuhitimishwa kwamba mass production inaweza kufanywa nchini Uturuki, cost advantage itapatikana, automotive au aviation certifications zitatimizwa, au same loss reduction itapatikana directly katika real converters.

Ni tatizo gani kuu la utafiti?

Silicon carbide (silicon carbide, SiC) MOSFETs ni semiconductor switches zinazozingatiwa katika high-voltage power electronics kutokana na low on-resistance na fast-switching characteristics. Hata hivyo si rahisi kuboresha forward on-resistance, reverse-conduction behavior, switching losses, breakdown voltage na gate-oxide reliability kwa wakati mmoja ndani ya single SiC MOSFET cell. Geometric change inayoboresha property moja inaweza kuzorotesha performance metric nyingine.

Katika conventional asymmetric trench MOSFET structure, trench-gate bottom na sehemu kubwa ya sidewalls zinalindwa na heavily doped P-well. P-well hii inalimit electric field inayotokea katika trench corners chini ya high voltage na hivyo kulinda gate oxide. Hata hivyo, kwa sababu protective P-well inafunga conduction path upande mmoja wa cell, only one MOS channel kwenye trench sidewall ndiyo inayotumika katika forward conduction. Hali hii inaweza kuongeza specific on-resistance.

Tatizo la pili ni kubeba reverse current. MOSFET inapofanya kazi katika third quadrant kwenye systems kama three-phase inverter, current inaweza kutiririka katika reverse direction. Katika conventional structure, current hii hupitia body diode inayofunguka kwa relatively high voltage kutokana na wide bandgap ya SiC. Body diode inapofanya kazi bipolarly, holes zinaingizwa katika drift region. Authors wanaunganisha process hii na risk ya bipolar degradation kwa long-term performance na stability.

Research question ni hii: je, kuweka two parallel MOS channels kwa forward direction na normally-off JFET channel inayofunguka kabla ya body diode kwa reverse direction ndani ya same asymmetric trench cell kunaweza kuboresha on-resistance, reverse-conduction voltage, reverse-recovery behavior na switching losses bila kuharibu blocking capability?

Design gap inayolengwa katika literature

Study inaorodhesha main reverse-conduction solutions zilizotumika awali kama external Schottky barrier diode, monolithic Schottky barrier diode, junction-barrier Schottky structure, heterojunction diode na MOS channel diode. Inaeleza kwamba external diodes zinaweza kuleta additional parasitic inductance na capacitance, Schottky contacts zinaweza kuongeza leakage current katika high temperature, heterojunction contacts zinaweza kuwa difficult to fabricate, na low-barrier MOS channel diodes zinaweza kuwa susceptible to early breakdown kwa sababu zinahitaji thin gate oxide.

Katika proposed approach, JFET channel isiyotegemea gate oxide inatumika kwa reverse current. Researchers walilenga channel hii ifunguke katika low reverse voltage lakini ibaki closed wakati wa forward conduction na blocking. Second MOS channel ndani ya same cell imeundwa kuunda additional electron path katika forward direction huku ikipunguza overlap area kati ya gate na drain.

IJDC-ATMOS structure inatofautianaje na conventional structure?

Figure 1 inalinganisha cross-sections za proposed IJDC-ATMOS na conventional C-ATMOS. Structures zote mbili zina 11 µm thick N-drift region, N-type substrate, drain metal, P-wells, N-type current-spreading layer na trench gate. Cell pitch imemodeliwa kuwa 3,2 µm katika devices zote mbili, trench depth 1,0 µm na gate oxide thickness 50 nm.

Katika C-ATMOS, forward-conduction channel ni Ch1 channel kwenye trench sidewall ya gate. Katika IJDC-ATMOS, pamoja na channel hii, kuna Ch2 channel yenye urefu wa 0,3 µm katika planar gate region chini ya trench. Ch1 na Ch2 zinaunganishwa in parallel katika forward conduction.

Upande wa opposite wa proposed structure, normally-off N-channel JFET imeundwa. JFET region inajumuisha surface P⁺ region, P-wells na N-type current-spreading layer iliyobaki kati yao. Source metal inawasiliana na P⁺ surface region na lower P-well na kufanya kazi kama control electrode ya JFET.

Dual forward-conduction channels zinafanyaje kazi?

Katika first quadrant, yaani chini ya positive drain-source voltage na positive gate-source voltage, Ch1 na Ch2 zinafunguka pamoja. Electrons zinaweza kutiririka sio tu kupitia Ch1 kwenye trench sidewall bali pia kupitia planar Ch2 chini ya trench. Parallel operation ya channels mbili inapanua total conduction path na kupunguza specific on-resistance.

Second function ya Ch2 ni kupunguza effective overlap area kati ya gate na drain regions. Geometric change hii inapunguza gate-drain capacitance na gate-drain charge inayohusiana na Miller region. Lower gate-drain charge inalenga kufanya gate voltage ibaki muda mfupi zaidi katika Miller plateau wakati wa switching na kumaliza switching faster.

Normally-off JFET inaundaje reverse-conduction path?

JFET channel imefafanuliwa kwa sehemu mbili, horizontal na vertical. Horizontal channel huundwa katika current-spreading layer kati ya P⁺ region na P-well; vertical channel huundwa kati ya neighboring P-wells. PN junctions katika regions hizi zinabana N-type layer iliyopo kati yao kwa depletion region na kuunda conduction-band energy barrier.

Katika forward conduction na forward blocking, energy barrier hii huiweka JFET channel katika pinched-off state. Hivyo JFET haitoi additional leakage au parallel current path kwenye normal forward operation ya dual MOS channels.

Katika third quadrant, negative gate-source na reverse drain-source condition zinapotumika, depletion region hupungua, conduction-band barrier hushuka na continuous unipolar electron path hufunguka kutoka N-type current-spreading layer hadi N⁺ source region. Kwa kuwa JFET imeundwa kufunguka katika voltage ya chini kuliko body diode, reverse current hubebwa kwanza kupitia JFET.

Three-dimensional conduction-band energy maps katika Figure 2 zinaonyesha mechanism hii. Katika forward-conduction condition, V_DS = 10 V na V_GS = 15 V, kuna distinct energy barrier katika JFET region. Katika reverse conduction, V_DS = −5 V na V_GS = −5 V zinapotumika, barrier inapotea kwa kiasi kikubwa na continuous electron path inatokea.

Kwa nini JFET channel widths ni muhimu?

Horizontal channel width W_L na vertical channel width W_V zinaamua JFET itafunguka katika reverse voltage gani na kama itabaki closed wakati wa blocking. Channel ikiwa too narrow, strong depletion inaweza kufanya reverse-conduction cut-in voltage ibaki high. Channel ikipanuliwa excessively, barrier inaweza kuwa too small na kusababisha unwanted conduction at zero bias au early breakdown.

Figure 3 inaonyesha reverse-conduction cut-in voltage kwa ujumla inapungua W_V inapoongezeka. W_V ikiwa small, effect ya change ya W_L ni limited kwa sababu opening inaamuliwa mainly na vertical-channel barrier. W_V inapokuwa larger, distinct barrier pia huundwa katika horizontal channel na change ya W_L inaathiri zaidi reverse-conduction cut-in voltage.

Hata hivyo graphs hizo hizo zinaonyesha breakdown voltage inashuka haraka W_L na W_V zinapokuwa excessively large. Text inasema katika W_L = 0,60 µm na W_V = 0,50 µm, JFET inaingia conduction at zero bias. Kwa hiyo researchers walichagua W_L = 0,45 µm na W_V = 0,50 µm.

Current-spreading layer ilioptimizeiwaje?

Width ya current-spreading layer W_CSL na doping concentration N_CSL huunda trade-off nyingine kati ya on-resistance na breakdown voltage. N_CSL au W_CSL inapoongezeka, depletion region inayoundwa na P regions hupungua na area ambayo electrons zinaweza kupita huongezeka. Matokeo yake R_on,sp hupungua.

Kinyume chake, wider and more highly doped current-spreading layer hubadilisha electric-field distribution katika high voltage na kupunguza breakdown voltage. Katika Figure 4, N_CSL iliscan-iwa katika 1,5×10¹⁶–3,5×10¹⁶ cm⁻³, na W_CSL katika 0,7–1,1 µm. Researchers walichagua N_CSL = 2,5×10¹⁶ cm⁻³ na W_CSL = 0,9 µm kwa kuzingatia static figure of merit.

Ni physical effects zipi zilizingatiwa katika Sentaurus TCAD model?

Proposed na conventional cells zilimodeliwa katika Sentaurus TCAD environment. Study inasema physical models hizi zilitumika katika simulations:

• Carrier-mobility saturation chini ya high electric field,
• Auger recombination,
• Okuto–Crowell impact ionization,
• Band-gap narrowing,
• Incomplete ionization,
• SiC/SiO₂ interface traps,
• Fixed charges katika SiC/SiO₂ interface.

Kuongeza interface traps na fixed charges kwenye model kunalenga kuepuka assumption ya ideal SiC/SiO₂ interface. Hata hivyo, detailed numerical values za trap-density distributions na fixed charges zilizotumika katika study hazijatolewa. Missing information hii inafanya iwe difficult kwa research group nyingine kureconstruct model exactly.

Forward-conduction results zinaonyesha nini?

Katika Figure 5, kwa V_GS = 15 V na I_DS = 200 A/cm², specific on-resistance ya C-ATMOS ilihesabiwa kuwa 2,49 mΩ·cm² na ya IJDC-ATMOS kuwa 1,69 mΩ·cm². Hivyo R_on,sp imepungua kwa approximately %32,1 katika proposed structure.

Katika electron-current-density maps, current ya conventional structure inaconcentrate only around Ch1, wakati IJDC-ATMOS inaonyesha two parallel paths kupitia Ch1 na Ch2. Same map pia inaonyesha JFET region inabaki katika low electron density. Result hii ina-support simulation mechanism kwamba JFET channel inabaki closed wakati wa forward conduction.

Reverse-conduction cut-in voltage ilibadilikaje?

Kwa V_GS = −5 V na magnitude ya reverse current density 50 A/cm², reverse-conduction cut-in voltage ya C-ATMOS body diode ilihesabiwa kuwa 2,82 V. JFET path ya IJDC-ATMOS ilianza conduction at 1,76 V. Absolute difference ni 1,06 V na relative reduction approximately %37,6.

Figure 6 inaonyesha reverse current inapitia body diode katika conventional structure, wakati katika IJDC-ATMOS current inafika source kupitia JFET channel. Kwa IJDC-ATMOS, reverse current density inapoongezeka kutoka 50 A/cm² hadi 300 A/cm², source-drain voltage inaongezeka kutoka 1,76 V hadi 2,66 V na depletion region katika JFET inapungua progressively.

Body diode na bipolar degradation zilitathminiwaje?

Figure 7 inaonyesha JFET region inabaki depleted katika forward conduction na 1200 V blocking conditions. Reverse current density ikiwa −100 A/cm², high hole density hutokea katika drift region ya conventional C-ATMOS, wakati hole density katika IJDC-ATMOS inabaki much lower.

Authors wanaeleza difference hii kwa C-ATMOS body diode kufunguka bipolarly na kuinject holes ndani ya drift region. Katika IJDC-ATMOS, reverse current inabebwa kwa unipolar electron conduction ya JFET, hivyo hole injection inasuppressiwa.

Result hii inaonyesha body-diode activation imesuppressiwa chini ya simulation conditions. Hata hivyo, kwa kuwa physical device haijatengenezwa na long-term bipolar-degradation experiment haijafanywa, phrase kwamba “bipolar degradation imeondolewa” haipaswi kutafsiriwa kama experimental reliability result.

Reverse-recovery charge imepungua kwa kiwango gani?

Reverse recovery ni transient process inayohitajika kuondoa stored carriers wakati polarity ya semiconductor junction inayobeba forward au reverse current inabadilishwa. High reverse-recovery current na charge zinaweza kuongeza switching loss na electrical stress katika circuit.

Katika Figure 8, reverse recovery imesimulateiwa kwa kutumia 600 V clamped-inductive double-pulse circuit. Circuit inaonyesha 5 nH parasitic inductance na 200 µH load inductance. IJDC-ATMOS na C-ATMOS zimelinganishwa kwa load-current conditions za 100, 200 na 300 A/cm².

Q_RR ya IJDC-ATMOS imeongezeka only kutoka 1,13 hadi 1,17 µC/cm² current inapoongezeka. Katika C-ATMOS, distinct increase kutoka 2,34 hadi 4,23 µC/cm² imeonekana katika same range. Hole-density curves across cross-section zinaonyesha hole density ya IJDC-ATMOS inabaki chini ya drift-region doping concentration ya 6×10¹⁵ cm⁻³.

Blocking voltage na temperature results

Proposed structure haikufikia only low on-resistance, bali pia higher breakdown voltage katika simulation. Table 2 inaripoti 1610 V kwa IJDC-ATMOS na 1485 V kwa C-ATMOS. Hivyo breakdown voltage ya proposed cell ni approximately %8,4 higher kuliko comparison structure.

Figure 9 inalinganisha blocking curves za devices katika 300 K na 450 K. Kuongezeka kwa breakdown voltage pamoja na temperature kumetafsiriwa katika study kama indication kwamba avalanche-breakdown mechanism ndiyo dominant. Temperature inapoongezeka, thermal energy ya carriers huongezeka na leakage current pia huongezeka.

Text inasema katika 450 K leakage current ya IJDC-ATMOS inatokana mainly na carriers wanaovuka JFET barrier thermally na I_BL inabaki chini ya 1×10⁻⁸ A. Hata hivyo vertical axis ya Figure 9 imetolewa kama current density kwa A/cm². Kuna clear reporting inconsistency kati ya ampere unit katika text na current-density unit katika graph.

Electric field katika gate oxide

Katika high voltage, electric field ya gate oxide kwenye trench bottom ni critical parameter kwa reliability ya SiC trench MOSFET. Katika simulation kwa V_DS = 1200 V, peak electric field katika gate oxide ya IJDC-ATMOS iliripotiwa kuwa 1,27 MV/cm, wakati ya C-ATMOS ilikuwa 1,92 MV/cm.

Electric-field insets za Figure 9 pia zinaonyesha higher local peak values katika SiC region. Hizi hazipaswi kuchanganywa na values za 1,27 na 1,92 MV/cm ndani ya gate oxide. Reliability assessment ya authors inategemea specifically electric-field value katika trench-bottom oxide.

Values hizi zimetokana na numerical electric-field distribution. Kwa kuwa hakuna time-dependent dielectric breakdown, constant gate-bias stress au cyclic reliability experiment iliyofanywa kwenye gate oxide, long device lifetime haijathibitishwa directly.

Capacitance na gate-drain overlap

Katika Figure 10, input capacitance C_iss na output capacitance C_oss zinaonekana kuwa close kwa structures zote mbili. Most distinct difference imetokea katika reverse-transfer au gate-drain capacitance.

Kwa V_DS = 800 V, C_GD ya IJDC-ATMOS ilihesabiwa kuwa 12,1 pF/cm² na ya C-ATMOS 20,9 pF/cm². Hii inalingana na %42,1 reduction. Researchers wanaunganisha reduction hii na kupungua kwa overlap area kati ya gate na drain kutokana na placement ya Ch2 kwenye trench bottom.

Katika study, high-frequency figure of merit inayotegemea C_GD imeelezwa kwa product hii:

\[ HF\text{-}FOM_{C_{GD}} = R_{on,sp} \times C_{GD} \]

Hapa R_on,sp ni specific on-resistance na C_GD ni gate-drain capacitance. Low value inaonyesha kwamba low static on-resistance na low capacitive switching load zimepatikana together. Value hii imetolewa kuwa 20,4 mΩ·pF kwa IJDC-ATMOS na 52,0 mΩ·pF kwa C-ATMOS, na %60,8 reduction imeripotiwa.

Gate-drain charge na Miller plateau

Figure 11 inalinganisha Q_GD values zilizotolewa kutoka Miller plateau ya gate-charge curves. Q_GD ya C-ATMOS ni 78,2 nC/cm² na ya IJDC-ATMOS ni 52,2 nC/cm². Proposed structure imepunguza gate-drain charge kwa %33,2.

High-frequency figure of merit inayotegemea Q_GD imetolewa kama:

\[ HF\text{-}FOM_{Q_{GD}} = R_{on,sp} \times Q_{GD} \]

R_on,sp×Q_GD ya IJDC-ATMOS ilihesabiwa kuwa 88,2 mΩ·nC, wakati ya C-ATMOS ilikuwa 194,7 mΩ·nC. Difference hii inalingana na %54,7 reduction.

Switching losses zilibadilikaje?

Figure 12 inalinganisha turn-on na turn-off transitions chini ya double-pulse circuit. Lower reverse-recovery charge ya IJDC-ATMOS imepunguza current-voltage overlap katika turn-on transition; lower C_GD na Q_GD zimefupisha turn-off time.

Total switching loss imeelezwa kama jumla ya turn-on na turn-off losses katika study results:

\[ E_{sw} = E_{on} + E_{off} \]

Kwa IJDC-ATMOS, 1,52 + 0,74 = 2,26 mJ/cm², na kwa C-ATMOS, 3,16 + 1,11 = 4,27 mJ/cm².

Overall comparison ya proposed na conventional structure

Strengths za study ni zipi?

• Forward conduction, reverse conduction, blocking, capacitance, gate charge, reverse recovery na switching behavior zimechunguzwa kwenye same device model.
• Sio only general cross-section ya new structure, bali operating mechanism imeonyeshwa kwa conduction-band, space-charge, electron-current na hole-density maps.
• Horizontal na vertical JFET channel widths zimescan-iwa kwa kuzingatia trade-off kati ya reverse-conduction cut-in voltage na breakdown voltage.
• Width na doping concentration ya current-spreading layer zimeoptimizeiwa kwa separate parametric analyses.
• Proposed na conventional device zimelinganishwa kwa same basic cell dimensions na drift-region properties.
• SiC/SiO₂ interface traps na fixed charges zimejumuishwa katika simulation model.
• Double-pulse na reverse-recovery simulations zimekamilisha static device results kwa dynamic switching metrics.

Limitations za study ni zipi?

• Study inategemea entirely Sentaurus TCAD simulation; physical IJDC-ATMOS haijatengenezwa.
• Electrical results hazijavalidateiwa kwa laboratory measurements.
• Fabrication flow, mask steps, ion implantation, epitaxy, oxidation na contact metallization hazijatolewa in detail.
• Sensitivity ya JFET region na lower planar channel kwa fabrication tolerances haijachunguzwa.
• SiC/SiO₂ interface-trap na fixed-charge values hazijaripotiwa in detail.
• Threshold voltage, channel mobility na temperature-dependent on-resistance hazijawasilishwa in detail.
• Short-circuit withstand, avalanche energy, gate-oxide lifetime na time-dependent dielectric breakdown hazijaanaliziwa.
• Parasitic cell-to-cell interaction, three-dimensional edge termination na real chip layout hazijamodeliwa.
• Double-pulse results haziwakilishi fully real package inductance, bond wire, thermal impedance na driver-circuit effects.
• 450 K result ni numerical temperature simulation; haionyeshi long-term high-temperature operating life.
• Hakuna statistical repetition, manufacturing distribution au process-variability analysis.
• Cost, chip area, manufacturing yield na commercial scalability hazijatathminiwa.

Reporting na editing issues katika text

• Some source references katika introduction zinaonekana corrupted kama “Error! Reference source not found.”
• Katika bibliography, same integrated JFET study imerudiwa kama references 24 na 25.
• Switching-loss explanation inarefer “Figure 15(b)”; katika uploaded study relevant result iko Figure 12(b).
• High-temperature leakage current imeandikwa kwa amperes katika text, wakati corresponding graph axis inaonyesha current density kwa A/cm².
• Conclusion section inatumia definite statements kwamba bipolar degradation “imesuluhishwa” au “imeondolewa”; study haitoi experimental na long-term reliability validation.
• Ingawa inasemwa kwamba data haikutumika, study inazalisha numerous numerical simulation outputs. Statement hii inaweza kutafsiriwa kuwa hakuna external dataset iliyotumika; hata hivyo simulation files au numerical results hazijashareiwa.

Ni conclusions zipi zinaungwa mkono na study?

• Proposed IJDC-ATMOS geometry imeonyesha lower specific on-resistance kuliko conventional C-ATMOS ndani ya TCAD model iliyotumika.
• Second planar MOS channel imeunda parallel electron path pamoja na Ch1 katika forward conduction.
• Integrated JFET imefunguka katika lower reverse voltage kuliko body diode katika simulation.
• Unipolar reverse conduction kupitia JFET imepunguza hole injection na reverse-recovery charge katika simulation.
• Geometry ya lower planar channel imepunguza gate-drain capacitance na gate-drain charge.
• Proposed structure imeonyesha lower turn-on na turn-off loss chini ya double-pulse simulation iliyotumika.
• P-well protection imeweka peak field katika trench oxide kwenye 1,27 MV/cm wakati wa 1200 V blocking.

Ni conclusions zipi hazijathibitishwa?

• Haithibitishi physical manufacturability ya IJDC-ATMOS.
• Haionyeshi real chip itatoa all values zilizotolewa katika table.
• Haithibitishi bipolar degradation itaondolewa completely katika real devices.
• Haionyeshi experimentally kwamba gate oxide itabaki reliable katika long-term use.
• Haionyeshi total system loss itapungua %47,1 katika real inverter au power converter.
• Haitoi field success katika electric vehicles, renewable energy, aviation au industrial systems.
• Haitoi evidence kuhusu mass-production cost, manufacturing yield, patent status au commercial applicability.
• Haiundi peer-reviewed scientific consensus au independent laboratory validation.

Mbinu na Matokeo ya Utafiti

Source, device na analysis type

Main geometrical na doping parameters

Simulation flow

1. Conventional C-ATMOS na proposed IJDC-ATMOS cross-sections ziliundwa kwa same basic cell dimensions.
2. JFET W_L na W_V widths zilibadilishwa na conduction-band barrier, reverse-conduction cut-in voltage na breakdown voltage zikahesabiwa.
3. W_L = 0,45 µm na W_V = 0,50 µm values zinazozuia early breakdown na kupunguza reverse-conduction cut-in voltage zilichaguliwa.
4. N_CSL na W_CSL ziliscan-iwa na on-resistance, breakdown voltage na static figure of merit zikalinganishwa.
5. Forward na reverse I–V curves pamoja na electron-current densities zilihesabiwa.
6. Space-charge na hole-density maps zilitumika kuchunguza JFET kubaki closed katika forward direction na open katika reverse direction.
7. Reverse recovery na switching transitions zilisimulateiwa kwa double-pulse circuit.
8. Blocking na leakage behavior zilitathminiwa katika 300 K na 450 K.
9. C_GD na Q_GD zilitolewa kutoka capacitance na gate-charge curves.
10. All main results zililinganishwa na conventional C-ATMOS.

Main numerical results

• R_on,sp imepungua kutoka 2,49 mΩ·cm² hadi 1,69 mΩ·cm².
• V_cut-in imepungua kutoka 2,82 V hadi 1,76 V.
• BV imeongezeka kutoka 1485 V hadi 1610 V.
• Katika 200 A/cm² load current, Q_RR imepungua kutoka 3,42 µC/cm² hadi 1,15 µC/cm².
• C_GD imepungua kutoka 20,9 pF/cm² hadi 12,1 pF/cm².
• Q_GD imepungua kutoka 78,2 nC/cm² hadi 52,2 nC/cm².
• Peak electric field katika gate oxide imepungua kutoka 1,92 MV/cm hadi 1,27 MV/cm.
• E_on imepungua kutoka 3,16 mJ/cm² hadi 1,52 mJ/cm².
• E_off imepungua kutoka 1,11 mJ/cm² hadi 0,74 mJ/cm².
• Total switching loss imepungua kutoka 4,27 mJ/cm² hadi 2,26 mJ/cm².

Statistical na experimental evaluation limit

Study haina experimental group, physical sample count, manufacturing repeat, mean, standard deviation, confidence interval, p value au significance threshold. Results zilizotolewa ni deterministic TCAD outputs zilizopatikana chini ya fixed geometry na physical-model parameters. Kwa hiyo percentage improvements zinaonyesha difference kati ya device models mbili katika simulation; hazionyeshi expected distribution au statistical confidence katika devices zitakazotengenezwa.

Dokezo la Chanzo na Mbinu

Full original title ya study: A New SiC Asymmetric Trench MOSFET With Integrated JFET and Dual Forward Channels for Improved Forward, Reverse, and Switching Characteristics

Authors na order yao: Jinsong Liang, Chengxi Ding, Zhaopeng Bai, Hong-Ping Ma, Qing-Chun Zhang

Equal first author au equal contribution: Hakuna taarifa ya equal-first-author au equal-contribution katika version hii.

Corresponding author: Hong-Ping Ma

Institutional affiliations:

• Institute of Wide Bandgap Semiconductors and Future Lighting, College of Intelligent Robotics and Advanced Manufacturing, Fudan University, Shanghai, China
• Shanghai Research Center for Silicon Carbide Power Devices Engineering & Technology, Fudan University, Shanghai, China
• Institute of Wide Bandgap Semiconductor Materials and Devices, Research Institute of Fudan University in Ningbo, Ningbo, China

DOI: Hakuna DOI information katika version hii.

Journal: Peer-reviewed journal name haijatajwa katika version hii.

Original publisher: Original journal au publisher information haiwezi kuthibitishwa kutoka version hii.

Publication platform: SSRN

Publication year: Publication year haiwezi kuthibitishwa kutoka text.

Source type: Preprint research article inayotegemea numerical semiconductor-device simulation

Peer-review status: Study hii ni preprint na haijapitia peer review.

Official preprint link:https://ssrn.com/abstract=7195346

Makala hii ya Kiswahili imeandaliwa kwa kupitia title ya uploaded study, author na institution information, text, device cross-sections, circuit diagrams, conduction-band surfaces, parametric graphs, current na carrier-density maps, blocking curves, capacitance na gate-charge graphs, double-pulse results, tables na conclusion section. Hakuna experimental au commercial success claims ambazo hazipo katika study zilizoongezwa.

Main limitation ya study ni kwamba all results zinategemea Sentaurus TCAD simulations. Physical device haijatengenezwa; forward na reverse conduction, blocking, reverse recovery, switching, temperature na gate-oxide reliability hazijavalidateiwa experimentally. Study hii ni preprint ambayo haijapitia peer review; results zinapaswa kusomwa kwa kuzingatia limitations hizi.