Utafiti wa kitaaluma, lugha inayoeleweka

Verianla | Akademik Araştırmalardan Türkçe Ekonomi ve Bilim İçerikleri

27 Septemba 2026, Jumapili
VERİANLAUchapishaji huru wa sayansi
Fungua au funga menyu
...
Home / Sayansi Tumizi / Uhandisi / Uchambuzi na Uboreshaji wa Mkazo wa Mzunguko wa Joto katika Chipu Zilizopangwa za Kifurushi cha CSOP: Muundo wa Majaribio ya Orthogonal na Algoriti ya Kundi la Samaki Bandia
Uhandisi

Uchambuzi na Uboreshaji wa Mkazo wa Mzunguko wa Joto katika Chipu Zilizopangwa za Kifurushi cha CSOP: Muundo wa Majaribio ya Orthogonal na Algoriti ya Kundi la Samaki Bandia

Katika vifurushi vya chipu vya tabaka nyingi, coefficients za thermal expansion za nyenzo tofauti kama silicon, adhesive na ceramic hutofautiana. Kifurushi kinapopitia temperature cycles, kutolingana huku huzalisha thermo-mechanical stresses na kwa muda mrefu kunaweza kuchangia mechanisms za uharibifu kama chip cracking, interface separation na kupungua kwa connection reliability.

08/09/2026  Veri Anla Imetazamwa mara 27
Uchambuzi na Uboreshaji wa Mkazo wa Mzunguko wa Joto katika Chipu Zilizopangwa za Kifurushi cha CSOP: Muundo wa Majaribio ya Orthogonal na Algoriti ya Kundi la Samaki Bandia

Katika vifurushi vya chipu vya tabaka nyingi, coefficients za thermal expansion za nyenzo tofauti kama silicon, adhesive na ceramic hutofautiana. Kifurushi kinapopitia temperature cycles, kutolingana huku huzalisha thermo-mechanical stresses na kwa muda mrefu kunaweza kuchangia mechanisms za uharibifu kama chip cracking, interface separation na kupungua kwa connection reliability. Utafiti huu unachunguza thermal-cycling stress ya muundo wa chipu za silicon wa tabaka tatu ndani ya Ceramic Small-Outline Package (CSOP) kwa pamoja na finite-element analysis, physical strain measurement, orthogonal experimental design, analysis of variance, second-order regression na Artificial Fish Swarm Algorithm. Initial model iliwekwa kwenye thermal cycles nne kati ya −55°C na 125°C; katika hatua ya dwell ya 125°C ya cycle ya nne, maximum von Mises stress ilihesabiwa kuwa 25.148 MPa kwenye bottom chip na maximum equivalent strain kuwa \(2.464\times10^{-4}\). Katika strain-rosette measurements kwenye physical CSOP sample, tofauti za experiment–simulation katika strain components tatu zilibaki katika kiwango cha %5.975–7.515. Kisha geometric parameters sita zilichunguzwa katika levels tano kila moja kwa \(L_{25}(5^6)\) orthogonal design na finite-element analyses 25 tofauti zikafanywa. Kwa mujibu wa Range analysis na ANOVA, mpangilio wa athari kwa thermal-cycling stress ni chip thickness > chip length > adhesive thickness > chip width > top-chip length > top-chip width. Chanzo kinaripoti kuwa parameters nne za kwanza ni significant katika %99 confidence level. Second-order regression model iliyoundwa kwa parameters hizi nne ina \(R^2\) ya 0.992. Artificial Fish Swarm Algorithm ilibainisha 5.00 mm chip length, 3.00 mm chip width, 0.30 mm chip thickness na 0.06 mm adhesive thickness kuwa optimum. Regression model ilitabiri stress ya 14.679 MPa huku finite-element model mpya ikitoa 14.408 MPa, na tofauti kati yao ilikuwa %1.88. Chanzo kinatumia orthogonal-design point ya 16.983 MPa kama reference ya “before optimization” na kuripoti stress reduction ya 2.575 MPa au %15.16; hata hivyo, kwa kuwa stress ya initial baseline FEA model ya makala ni 25.148 MPa, hizi values mbili za kuanzia lazima zitenganishwe.

Kwa nini thermal stress hutokea katika stacked chips za kifurushi cha CSOP?

Silicon chips, insulating adhesive na ceramic package base ndani ya CSOP hazipanuki kwa kiwango sawa chini ya mabadiliko yale yale ya joto. Kwa kuwa materials zimeunganishwa, free expansion huzuiwa na thermo-mechanical stress hutokea kati yao. Utafiti huu unachunguza hasa jinsi silicon–adhesive geometry inavyobadilisha magnitude ya stress hii.

Initial CSOP model iliundwaje?

Model ina sehemu mbili kuu: CSOP20 ceramic package base na multilayer stacked-chip assembly ndani yake. Stack ina bottom na middle silicon chip, top chip ndogo zaidi, spacer ya kati na adhesive layer zinazounganisha vipengele hivi. Spacer hutoa clearance inayohitajika kwa wire bonding kati ya bottom na middle chip.

ComponentDimension
Bottom chip6 × 4 × 0.2 mm
Middle chip6 × 4 × 0.2 mm
Top chip3 × 2 × 0.2 mm
Adhesive layer0.05 mm
CSOP20 outer size12.64 × 7.5 × 2.6 mm
CSOP20 cavity8.04 × 5.18 × 1.6 mm

External leads za kifurushi cha CSOP20 hazikujumuishwa kwenye finite-element model.

Sifa za nyenzo

MaterialDensityCTEYoung modulusPoissonThermal conductivitySpecific heat
Silicon2300 kg/m³2.3×10⁻⁶ K⁻¹169 GPa0.26131 W/mK700 J/kgK
Insulating adhesive1300 kg/m³3.5×10⁻⁶ K⁻¹5 GPa0.380.2 W/mK550 J/kgK
Ceramic base2450 kg/m³6.5×10⁻⁶ K⁻¹260 GPa0.2324.7 W/mK880 J/kgK

Mesh independence ilikaguliwaje?

Chip mesh size ilipunguzwa kwa mpangilio hadi 0.20, 0.15 na 0.10 mm. Maximum thermal-cycling stress:

Mesh sizeStressChange relative to previous solution
0.20 mm25.017 MPa—
0.15 mm25.093 MPa0.304%
0.10 mm25.148 MPa0.219%

Kwa kuwa mabadiliko katika refinement steps mbili yalibaki chini ya %0.5, utafiti ulitumia mesh size ya 0.10 mm. Final model ina 223,215 node na 49,080 SOLID185 element.

Thermal cycle inatumikaje?

Thermal cycle huanza 25°C, hupanda hadi 125°C, kisha hushuka hadi −55°C na kurudi tena kwenye starting temperature. Heating na cooling rate ni 0.5°C/s, na dwell time katika high na low temperature ni sekunde 600.

ParameterValue
Maximum temperature125°C
Minimum temperature−55°C
Temperature range180°C
Heating/cooling rate0.5°C/s
High-temperature dwell600 s
Low-temperature dwell600 s
One cycle1920 s
Number of cycles4
Total time7680 s
Stress-free reference25°C

Corner points nne kwenye lower surface ya Ceramic base ziliwekwa fixed. Evaluation variables ni von Mises equivalent stress na equivalent strain.

Maximum thermal stress inajikusanya wapi?

Mwishoni mwa 125°C dwell ya cycle ya nne, maximum stress hutokea kwenye bottom silicon chip. Stress field hujikusanya hasa katikati ya chip na maeneo ya kingo ya chip–adhesive interface.

Initial FEA resultValue
Maximum von Mises stress25.148 MPa
Maximum equivalent strain\(2.464\times10^{-4}\)
Critical componentBottom chip

Finite-element model ilikaguliwaje kwa experiment?

Physical stacked-silicon sample inayolingana na initial geometry ilitengenezwa. Adhesive layer thickness ilidhibitiwa kwa kutumia 0.05 mm feeler gauge. Sample iliwekwa kwenye CSOP package na kuwekewa temperature cycle ileile ndani ya thermal cycling chamber.

Measurement system ina computer, DH3817 dynamic resistance strain measurement system na thermal cycling chamber. Three-element strain-gauge rosette iliunganishwa kwenye upper surface ya chip.

Directional strains zilizopimwa mwishoni mwa 125°C dwell ya cycle ya nne:

\[ \varepsilon_{0^\circ}=6.214\times10^{-5} \]

\[ \varepsilon_{45^\circ}=8.476\times10^{-5} \]

\[ \varepsilon_{90^\circ}=7.146\times10^{-5} \]

ziliripotiwa.

Two-dimensional strain transformation relation:

\[ \varepsilon_\theta= \frac{\varepsilon_x+\varepsilon_z}{2} + \frac{\varepsilon_x-\varepsilon_z}{2}\cos2\theta + \frac{\gamma_{xz}}{2}\sin2\theta \]

ilitumika na:

\[ \varepsilon_x=\varepsilon_{0^\circ} \]

\[ \varepsilon_z=\varepsilon_{90^\circ} \]

\[ \gamma_{xz}=2\varepsilon_{45^\circ} -\varepsilon_{0^\circ} -\varepsilon_{90^\circ} \]

zikapatikana.

ComponentMeasurementFEARelative error
\(\varepsilon_x\)6.214×10⁻⁵5.747×10⁻⁵7.515%
\(\varepsilon_z\)7.146×10⁻⁵7.573×10⁻⁵5.975%
\(\gamma_{xz}\)3.592×10⁻⁵3.330×10⁻⁵7.294%

Matokeo haya yanaunga mkono kwamba FEA ina reasonable agreement na strain response katika measurement point. Hata hivyo, strain gauge haipo katika bottom-chip region ambako maximum stress iko; kwa hiyo 25.148 MPa peak stress haikupimwa moja kwa moja kwa experiment.

Mbinu na Matokeo

Ni parameters gani sita zilizotumika katika orthogonal experimental design?

LevelChip lengthChip widthTop-chip lengthTop-chip widthChip thicknessAdhesive
15.03.02.01.00.100.040
25.53.52.51.50.150.045
36.04.03.02.00.200.050
46.54.53.52.50.250.055
57.05.04.03.00.300.060

Bottom na middle chip zilichukuliwa kuwa na length na width sawa; thickness ileile ilitumika kwa chips zote tatu. Kwa kutumia orthogonal array, badala ya kuhesabu combinations zote \(5^6=15,625\), representative FEA configurations 25 ziliundwa.

Range analysis ilibainisha parameter gani kuwa critical zaidi?

FactorRange \(R\)Order of influence
Chip thickness15.5361
Chip length7.6432
Adhesive layer thickness4.3113
Chip width3.8694
Top-chip length1.2195
Top-chip width0.8656

Matokeo haya yanaonyesha kuwa chip thickness ina athari kubwa zaidi kwa uwazi kuliko geometric variables nyingine.

Matokeo ya ANOVA

FactorF-ratio\(F_{0.01}\)Source interpretation
Chip length69.39915.977Highly significant
Chip width19.07615.977Highly significant
Top-chip length1.98415.977Not significant
Chip thickness296.15615.977Highly significant
Adhesive thickness24.44515.977Highly significant

Kwa kuwa hakuna independent replication katika orthogonal design, chanzo kilipool factor ya top-chip-width yenye athari ndogo zaidi kama error term. Kwa hiyo inapaswa kuzingatiwa kuwa significance results zinategemea error-modeling assumption hii.

Correlation analysis

FactorPearson \(r\)Source trend
Chip length0.40954Stress inaelekea kuongezeka kadiri length inavyoongezeka
Chip width0.21374Stress inaelekea kuongezeka kadiri width inavyoongezeka
Chip thickness−0.82102Stress inapungua kwa uwazi kadiri thickness inavyoongezeka
Adhesive thickness−0.23364Stress inaelekea kupungua kadiri thickness inavyoongezeka

Regression model iliundwaje?

Factors nne zilizopatikana kuwa significant katika ANOVA:

\[ X_1=\text{çip uzunluğu} \]

\[ X_2=\text{çip genişliği} \]

\[ X_3=\text{çip kalınlığı} \]

\[ X_4=\text{adhesive thickness} \]

zilichaguliwa na general second-order polynomial model:

\[ Y= \alpha_0+ \sum_{i=1}^{n}\alpha_iX_i+ \sum_{i=1}^{n}\alpha_{ii}X_i^2+ \sum_{i=1}^{n-1}\sum_{j=i+1}^{n}\alpha_{ij}X_iX_j+\varepsilon \]

ilitumika.

Katika printed Equation (5), chanzo kinatoa:

\[ \begin{aligned} Y=&90.129-7.162X_1-3.756X_2-145.443X_3-979.382X_4\\ &+0.358X_1^2-0.124X_2^2+271.358X_3^2+2545.318X_4^2\\ &+0.983X_1X_2-8.723X_1X_3+90.877X_1X_4+4.090X_2X_3 \end{aligned} \]

. Hata hivyo, paragraph inayofuata mara moja inasema model ina interaction terms sita na coefficients 15 kwa jumla, huku formula iliyochapishwa ikionyesha interaction nne tu na coefficients 13 kwa jumla. Coefficients za \(X_2X_4\) na \(X_3X_4\) hazionekani katika chanzo. Kwa hiyo numerical regression equation haionekani kuwa fully reproducible.

Chanzo kinaripoti kwa model:

\[ R^2=0.992 \]

na:

\[ p<0.0001 \]

.

Artificial Fish Swarm Algorithm ilitumikaje?

Kila artificial fish inawakilisha possible solution inayoundwa na geometric parameters nne:

\[ X=(X_1,X_2,X_3,X_4). \]

Search bounds:

\[ 5\le X_1\le7 \]

\[ 3\le X_2\le5 \]

\[ 0.1\le X_3\le0.3 \]

\[ 0.04\le X_4\le0.06. \]

ParameterValue
Artificial-fish population2000
Maximum iteration3000
Visual distance0.5 → 0.05
Step length0.1 → 0.005
Crowding factor0.618
Convergence criterion\(<10^{-8}\) change, 50 consecutive iterations

Optimum geometry

ParameterOptimum
Chip length5.00 mm
Chip width3.00 mm
Chip thickness0.30 mm
Adhesive thickness0.06 mm

Regression prediction:

\[ Y_{reg}=14.679\ {\rm MPa} \]

na finite-element verification mpya:

\[ Y_{FEA}=14.408\ {\rm MPa} \]

.

Chanzo kinatoa relative error kati ya matokeo mawili kama:

\[ 1.88\% \]

.

Optimization gain inapaswa kutafsiriwaje?

ConditionStressNote
Initial baseline CSOP FEA model25.148 MPa6×4×0.2 mm, adhesive 0.05 mm
Source “before optimization” value16.983 MPaOrthogonal design No.2
AFSA regression prediction14.679 MPaSurrogate optimum
Optimize FEA verification14.408 MPaFinal numerical verification

Chanzo kinatumia tofauti ya 16.983 MPa → 14.408 MPa kuripoti 2.575 MPa na %15.16 stress reduction. Hata hivyo, 16.983 MPa si matokeo ya initial baseline model; ni orthogonal combination ya pili katika Table 4. Kwa hiyo %15.16 inapaswa kuhifadhiwa kama source result lakini isielezwe upya kama “reduction relative to original CSOP design”.

Je, matokeo haya yanaonyesha real service life?

Hapana. Utafiti una-optimize maximum von Mises stress katika thermal cycles nne. Adhesive viscoelasticity, creep, interface cohesive damage, crack propagation au cycles-to-failure model hazijaripotiwa. Kwa hiyo maximum stress ya chini inaweza kuwa mechanical design indicator ya reliability bora; lakini utafiti huu hauhesabu service life moja kwa moja.

Matokeo yanayoungwa mkono na utafiti

  • Stacked-chip geometry ndani ya CSOP hubadilisha thermal-cycling stress kwa kiasi kikubwa.
  • Katika initial FEA model, maximum stress hujikusanya kwenye bottom chip na hasa karibu na chip–adhesive interface.
  • Strain-rosette measurements zilionyesha tofauti ya chini ya %10 dhidi ya local strain response ya initial FEA.
  • Kati ya parameters zilizochunguzwa, chip thickness ina strongest effect.
  • Chip length na width zina positive correlation na stress, huku chip thickness na adhesive thickness zikiwa na negative correlation.
  • Katika source ANOVA, parameters nne zilipatikana significant katika %99 confidence level.
  • Second-order regression model ililingana na design data kwa \(R^2=0.992\).
  • AFSA ilipata combination ya 5.00 mm, 3.00 mm, 0.30 mm na 0.06 mm kuwa optimum.
  • Regression optimum ilikuwa 14.679 MPa, huku independent new FEA point ikitoa 14.408 MPa.
  • Chanzo kinaripoti %15.16 stress reduction relative to reference yake ya 16.983 MPa.

Majumuisho yasiyoungwa mkono na utafiti

  • Optimized CSOP configuration haikujaribiwa katika physical thermal-cycling experiment.
  • 14.408 MPa maximum stress si experimental strain gauge measurement.
  • Matokeo ya cycles nne si long-term thermal-fatigue life prediction.
  • Thamani ya \(R^2=0.992\) ya regression model si performance kwenye independent large test set.
  • Haijathibitishwa kuwa AFSA ilipata mathematical global optimum kwa geometries zote zinazowezekana.
  • ANOVA haina independent repeated-error term.
  • Adhesive creep, delamination na fracture mechanics hazijatathminiwa moja kwa moja katika model hii.
  • Thamani ya 16.983 MPa si sawa na 25.148 MPa result ya original initial FEA.
  • Kwa sababu ya interaction coefficients zinazoonekana kukosekana katika source Equation 5, regression model haiwezi kuzalishwa tena kikamilifu kwa kujitegemea.

Maelezo ya Chanzo na Mbinu

Utafiti asilia:Thermal Cycling Stress Analysis and Optimization of CSOP-Packaged Stacked Chips Based on Orthogonal Experimental Design and the Artificial Fish Swarm Algorithm.

Waandishi: Shuaiqi Ge, Chunyue Huang, Gui Wang na Ying Liang.

Taasisi: School of Mechanical and Electrical Engineering, Guilin University of Electronic Technology; Key Laboratory of Interior Layout Optimization and Security, Institutions of Higher Education of Sichuan Province, Chengdu Normal University; College of Electronic Engineering, Chengdu Aeronautic Polytechnic.

SSRN Contact Author: Chunyue Huang.

DOI: 10.2139/ssrn.7208078.

SSRN ID: 7208078.

Publication status: Preprint ya kurasa 14 iliyochapishwa SSRN tarehe 30 Julai 2026 na haijapitia peer review.

Aina ya utafiti: Finite-element thermomechanical simulation, physical strain validation, orthogonal experimental design, range analysis, ANOVA, correlation analysis, nonlinear polynomial regression na Artificial Fish Swarm Algorithm based numerical optimization.

Physical validation: Katika initial CSOP geometry, in-plane strain components tatu zilipimwa kwa strain-gauge rosette na tofauti ya %5.975–7.515 ikapatikana dhidi ya simulation. Peak von Mises stress haikupimwa moja kwa moja.

Thermal loading: −55°C–125°C, 0.5°C/s heating/cooling, 600 s high/low dwell, cycles nne na total 7680 s.

Mesh: 0.1 mm chip element size, 223,215 node, 49,080 SOLID185 element.

Orthogonal design: Factors sita, levels tano, \(L_{25}(5^6)\), total finite-element configurations 25.

ANOVA limitation: Kwa kuwa hakuna independent repeated error katika design, top-chip-width factor yenye lowest effect ilipooliwa kwenye error term. %99 significance ilihesabiwa kwa assumption hii.

Regression QA: Source text inasema model ina constant moja, linear nne, quadratic nne na interaction sita, jumla coefficients 15. Katika printed Equation 5, interaction nne tu na coefficients 13 kwa jumla zinaonekana; coefficients za \(X_2X_4\) na \(X_3X_4\) hazionekani.

Optimization: AFSA population 2000, maximum 3000 iteration, visual 0.5→0.05, step 0.1→0.005 na crowding factor 0.618.

Optimum: 5.00 mm chip length, 3.00 mm chip width, 0.30 mm chip thickness na 0.06 mm adhesive thickness.

Optimum result: Regression 14.679 MPa; finite-element verification 14.408 MPa; source relative difference 1.88%.

Source baseline note: Initial baseline model inatoa 25.148 MPa, huku “before optimization” value katika optimization section ikiwa 16.983 MPa na ikilingana na Orthogonal No.2 configuration katika Table 4. %15.16 reduction iliyoripotiwa na chanzo imehesabiwa relative to value hii ya pili.

Reference QA: Thermal cycling profile imetajwa katika text kama MIL-STD-883C [21]; lakini [21] katika bibliography ni 2025 PoP stacked-solder-joint paper ya Gao et al. Bibliographic entry ya standard hailingi na reference number.

Modeling limitation: Source property set hairipoti adhesive viscoelasticity/creep, cohesive-zone delamination, silicon cracking au fatigue-damage law. Objective ya utafiti ni maximum thermal-cycling stress, si direct service-life prediction.

Ufadhili: National Natural Science Foundation of China, Grant 62164002 na Chengdu Normal University Key Laboratory Foundation, Grant SNKJ202602.

Data availability / conflict of interest: Hakuna separate Data Availability au Conflict of Interest statement inayoonekana katika uploaded preprint; hakuna statement ya nje ya chanzo iliyoongezwa.

Hakimiliki: SSRN record information inaonyesha all rights reserved. Badala ya kutumia Figure 1–11 moja kwa moja, CSOP package, stacked-chip stress map, thermal cycle na AFSA optimization flow zinapaswa kuchorwa upya kwa asili kwa Verianla.


Shiriki:

Maoni huchapishwa baada ya kukaguliwa.Maoni yako yatapitia mchakato wa idhini na yataonekana yakikubaliwa.

Acha maoni

Anwani yako ya barua pepe haitachapishwa. Sehemu za lazima zimewekewa alama ya *

Your experience on this site will be improved by allowing cookies Cookie Policy